Referring to FIG. 1, a conventional current mirror circuit 10 is shown. The circuit 10 includes a MOSFET M1, a MOSFET M2, an input current Iin, and an output current Io. The MOSFET M1 is connected as a diode that operates in saturation. The MOSFET M1 has a channel that carries the input current Iin. The MOSFET M2 also operates in saturation. The MOSFET M2 has a channel that carries the output current Io. The gates of the MOSFET M1 and the MOSFET M2 are connected together to ensure identical control voltages (i.e., gate to source voltages). Identical control voltages on the MOSFET M1 and the MOSFET M2 results in the input current Iin being mirrored to the output current Io. The ratio of the input current to the output current (Io/Iin) depends on the dimensions of the MOSFET M1 and the MOSFET M2.
To simplify the analysis in this context, if the MOSFETs M1 and M2 are considered to have the same dimensions, then Io=Iin.
The term “saturation” refers to an operating condition which applies to the following equation EQ1:Vds>Vgs−Vth=Vov  (EQ1)where:
Vds is a drain to source voltage,
Vgs is a gate to source voltage (control voltage),
Vth is a threshold voltage, and
Vov is an overdrive voltage necessary to establish current flow through the channel.
The input voltage headroom is defined by the following equation EQ2:Vvh=Vvdda−Vgs,M1=Vvdda−(Vth,M1+Vov,M1)  (EQ2)where:
Vvh represents input voltage headroom, and
Vvdda is the positive supply voltage minus ground supply voltage.
Referring to FIG. 2, a diagram of a circuit 20 is shown. The circuit 20 has improved input voltage headroom compared with the circuit 10 and is described in U.S. Pat. No. 5,394,079. The circuit 20 adds an N-type MOSFET M3 and a bias current Ib. A P-type current mirror includes a MOSFET M1 and a MOSFET M2. The N-type MOSFET M3 and the bias current Ib combine to form a level shifter. The bulk connection Vb is used to adjust the threshold voltage of the MOSFET M3.
The input voltage headroom of the circuit 20 is defined by the following equation EQ3:Vvh=Vvdda−Vgs,M1+Vgs,M3=Vvdda−(Vth,M1+Vov,M1)+Vgs,M3  (EQ3)The following equation EQ4 ensures the MOSFET M1 works in saturation mode:Vds,M1=Vvdda−Vvh=Vth,M1+Vov,M1−Vgs,M3>Vov,M1  (EQ4)The threshold voltage of the MOSFET M1 minus the gate to source voltage of the MOSFET M3 should be greater than zero.
The circuit 20 implements the MOSFET M1 and the MOSFET M3 as different types of MOSFETs, having different threshold voltages and different values. The gate to source voltage of the MOSFET M3 must be adjusted to satisfy the saturation condition. For the circuit 20, the bulk of the N-type MOSFET M3 is connected to a bias voltage Vb. The bulk bias voltage Vb is adjusted by a voltage bias generator circuit to a value higher than ground potential to help reduce the gate to source voltage of the MOSFET M3. Such an implementation has very limited headroom and has problems when the PN junction of the MOSFET M3 is turned on.
Even when adjusting the bias voltage Vb, the circuit 20 faces other problems. Since the MOSFET M1 and the MOSFET M3 use different types of transistors, different process variations, temperature changes and trends will occur, even if the MOSFET M1 and the MOSFET M3 have the same trends but have different velocities. By using the circuit 20, the value of the gate to source voltage of the transistor M3 should be a small value which gives an enough margin for the MOSFET M1 to operate in saturation. A small gate to source voltage on the transistor M3 ultimately deteriorates the efficiency of the circuit 20.
It would be desirable to implement a current mirror with sufficient headroom when operating in a low voltage application.